The present invention relates generally to integrated circuit devices and fabrication methods therefor, and, more particularly, to integrated circuit devices that include resistor patterns and fabrication methods therefor.
As semiconductor devices become more highly integrated, the width and spacing of conductive patterns, such as cell gate electrodes, may be reduced. If the thickness of conductive patterns is not reduced corresponding to the reduction of the width and the spacing, then it may be difficult to perform photolithographic etching to form conductive patterns. In addition, patterned conductive patterns typically have a high aspect ratio so that a subsequent process, such as a gap-fill process, may also have technical problems.
In particular, in the field of FLASH memory devices, the height of gate electrodes may increase due to a floating gate electrode. Accordingly, the above-mentioned problems may be a concern in the field of FLASH memory devices. Furthermore, the dispersion of electrical characteristics (e.g., a threshold voltage of cell transistors) may result due to coupling between two adjacent floating gate electrodes. As a result, product quality may deteriorate.
To address some of these problems, methods for reducing the thickness of the gate electrode and the floating gate electrode have been suggested. This approach, however, may have a disadvantage in that the contact resistance of a resistor may be increased.
FIG. 1 is a cross-sectional view that illustrates a conventional method for fabricating a FLASH memory device resistor. Referring now to FIG. 1, a device isolation layer 20 is formed in a predetermined region of a semiconductor substrate 10. A lower conductive pattern 30, a gate interlayer dielectric layer 40, and an upper conductive pattern 50 are sequentially stacked on the device isolation layer 20.
The upper conductive pattern 50 includes first and second conductive patterns 52 and 54, which are sequentially stacked. Conventionally, the lower conductive pattern 30 and the first upper conductive pattern 52 are formed of polysilicon, and the second upper conductive pattern 54 is formed of metallic material layer, such as tungsten silicide. The second upper conductive pattern 54 may be constructed with a control gate of a FLASH memory; therefore, the second upper conductive pattern 54 may be formed of a metallic material having a low resistivity, such as tungsten so as to reduce a signal-delay of a word line. However, the resistivity of the second upper conductive pattern 54 may be too low to form a resistor pattern having a required resistance. Thus, the lower conductive pattern 30 may be formed using polysilicon for a FLASH memory device resistor.
An interlayer dielectric layer 70 is formed on a semiconductor substrate where the upper conductive pattern 50 is formed. The interlayer dielectric layer 70 is patterned to form an opening 75 exposing a top surface of the lower conductive pattern 30. The opening 75 is formed at both sides of the lower conductive pattern 30. The opening 75 is filled with a contact plug 80 that is connected to the lower conductive pattern 30. The contact plug 80 may be formed using metallic materials, such as tungsten, and is connected to a metallic interconnection 85.
The lower conductive pattern 30 is used as a floating gate electrode in a cell array region. Thus, the thickness of the lower conductive pattern 30 may become thin as discussed above. An anisotropic etching process for forming the opening 75 may be performed using an over-etch method to reduce the likelihood of a connection failure (e.g., not-open phenomenon) between the contact plug 80 and the lower conductive pattern 30. Additionally, to simplify processing, an etching process for forming the opening 75 and an etching method for forming a bit line contact hole are performed at the same time. The thickness of the interlayer dielectric layer 70 is relatively thicker in the bit line contact hole than in the opening 75 due to the lower conductive pattern 30. Owing to this difference of thickness, the contact area between the contact plug 80 and the lower conductive pattern 30 may be changed. For example, if the opening 75 penetrates the lower conductive pattern 30 with low thickness to expose the device isolation layer 20, only the sidewalls of the contact plug 80 are in contact with the lower conductive pattern 30 (see FIG. 2). If the opening 75 does not penetrate the lower conductive pattern 30, then the top and lateral portions of the contact plug 80 are in contact with the lower conductive pattern 30 (see FIG. 3).
If different kinds of materials are used, a connection resistance between them may be highly influenced by contact area. As previously mentioned, if the contact plug 80 is formed of tungsten, and the lower conductive pattern 30 is formed of polysilicon, then the contact resistance may vary depending on a variation of contact area between the contact plug 80 and the lower conductive pattern 30. Specifically, if the contact plug 80 is formed of tungsten, a general barrier metal layer including titanium and titanium nitride may react with the polysilicon of the lower conductive pattern 30. As a result, problems may be incurred due to the formation of insulated titanium silicide. To reduce the likelihood of these problems, another mask pattern may be used in the etching process. The addition of the mask pattern may increase processing costs, however.